1. Field of the Invention
The present invention relates to a test apparatus, particularly a test apparatus for testing a device under test for synchronizing a data signal with a clock signal to output the same.
2. Related Art
Conventionally, there is a semiconductor memory for writing a data signal inputted together with a clock signal in synchronism with each other and outputting the data signal together with the clock signal in synchronism with each other to receive/transmit the data signal at the timing of the clock signal. Such semiconductor memory can not desirably operate unless the timing at which the clock signal is outputted and the timing at which the data signal is outputted are preciously synchronized. Therefore, when such semiconductor memory is tested, it has been determined that the semiconductor memory is passed or failed by detecting the change point of the clock signal and the change point of the data signal, which are outputted from the semiconductor memory being a device under test using a multi-strobe signal to detect the phase difference between the clock signal and the data signal and comparing the phase difference with the spec, as disclosed in Japanese Application Publication No. 2001-201532 and No. 2001-356153.
The semiconductor memory such as a synchronous device outputs a plurality of data signals in synchronism with the clock signal. Therefore, it is necessary that data indicative of the change point of the clock signal is separately provided to phase difference detection means which are installed corresponding to the plurality of data signals in order to detect the phase difference between each of the data signals and the clock signal in parallel. However, it takes time to provide data of the change point of the clock signal to the plurality of phase difference detection means because transmission delay times are occurred in a distribution circuit for distributing data indicative of the change point of the clock signal and a transmission path for transmitting data indicative of the change point of the clock signal to the phase difference detection means. Therefore, the phase difference between the clock signal and the data signal sometimes can not be detected in real time and in synchronism with outputting by the device under test.